1. Field of the Invention
The present invention relates to the field of integrated circuit frequency multiplier circuits that utilize a phase-locked loop (PLL) circuit to generate a fixed multiple of an input frequency.
2. Prior Art
A fixed multiple of an input frequency commonly must be generated in applications such as frequency synthesizers, video signal generation, obtaining a clock frequency, FM detection/demodulation, pulse synchronization, and in numerous other applications. A PLL frequency multiplier circuit is commonly used to generate an output signal having a frequency that is a fixed multiple of the frequency of the input signal. Unfortunately, the output signal of traditional PLL frequency multiplier circuits is not a square-wave, especially when operating at high frequencies. Additionally, there is a phase difference between the output signal and the input signal. These two problems make traditional PLL frequency multiplier circuits undesirable for some applications.
The past approaches in generating a fixed multiple of an input frequency using a PLL frequency multiplier have thus resulted in a non-square-wave output signal with a phase difference between the output signal and the input signal. Therefore, there exists a need for a PLL frequency multiplier that has a square-wave output signal with substantially no phase difference between the output signal and the input signal. The present invention provides a PLL frequency multiplier circuit having a square-wave output signal that is substantially in phase with the input signal.